1. Field of the Invention
The present invention relates to an electrically programmable non-volatile semiconductor memory with an improved reliability eliminating an erroneous operation of non-selected memory cells to be caused by voltage stress applied thereto.
2. Description of the Related Background Art
Data of an electrically erasable and programmable ROM (EEPROM) can be erased and programmed while it is being mounted on a circuit board. It is therefore easy to use as compared to an ultraviolet erase type EPROM. Demands for EEPROMs are rapidly increasing in the application to control memories, IC card memories and the like. As memory cells M for EEPROMs of a large capacity, three-layered polysilicon structure type non-volatile transistors are used each having a floating gate FG, a control gate CG and an erase gate EG like shown in FIG. 1. A number of such memory cells are disposed in a matrix form to constitute a memory cell array MA. In erasing data, a positive high voltage is applied to the erase gate EG to emit electrons stored in the floating gate FG toward the erase gate EG. In writing data, a high voltage is applied to the control gate CG and drain D of a selected memory cell M to inject electrons to the floating gate FG.
In writing data to EEPROM, it is conventional to set the erase gate to 0 V or V.sub.CC. Therefore, a voltage stress of the floating gate of a non-selected memory cell becomes large. Namely, the electric field between the floating gate and the erase gate or channel of a non-selected memory cell becomes great, resulting in erroneous operations such as electron injection (write error) from the erase gate or substrate to the floating gate, and electron emission (erase error) from the floating gate to the erase gate.
The voltage stress of a non-selected memory cell will be described in detail with reference to the cell pattern layout and equivalent circuit.
FIG. 2A is a plan view showing a memory cell pattern, FIG. 2B is a cross section taken along line A--A' of FIG. 2A, and FIG. 2C is a cross section taken along lien B--B' of FIG. 2A. In FIGS. 2A to 2C, reference numeral 11 represents a floating gate of a first polysilicon layer, reference numeral 12 represents an erase gate of a second polysilicon layer, and reference numeral 13 represents a control gate of a third polysilicon layer. The control gate 13 is used also at a memory cell word line. Reference numeral 14 represents a p-type substrate, reference numerals 15 and 16 represent a source and drain formed by n.sup.+ type diffusion layers on the substrate 14, and reference numeral 17 represents a contact hole. Reference numeral 18 represents a data line of an aluminum layer connected to the drain 16 via the contact hole 17. Reference numeral 19 represents a gate insulating film for the floating gate transistor portion, reference numeral 20 represents a gate insulating film between the floating gate 11 and erase gate 12, and reference numeral 21 represents a gate insulating film between the floating gate 11 and control gate 13. The gate insulating film 21 is made of a three-layered film of an oxide-nitride-oxide (O-N-O) structure. Reference numeral 22 represents a gate insulating film between the erase gate 12 and control gate 13, which has also the O-N-O structure. Reference numeral 23 represents an insulating film for the control gate transistor portion made of the third polysilicon layer. Reference numeral 24 represents a field insulating film, and reference numeral 25 represents an interlayer insulating film.
The fundamental operation of a memory cell having such a structure will be described next. As seen from FIG. 1, in writing data, a high voltage, e.g., +8 V, is applied to the drain 16, 0 V is applied to the source 15, a positive high voltage, e.g., 12 V, is applied to the control gate 13, and a power source voltage, e.g., 5 V, is applied to the erase gate 12. In this state, the hot electron effect occurs near the drain so that electrons generated by impact ionization are injected into the floating gate 11 to charge it negative. As a result, the threshold voltage of the memory cell rises. This condition is assumed as data "0".
In erasing data "0" written in a memory cell by injecting electrons in the floating gate 11, 0 V is applied to the source 15, drain 16 and control gate 13, and a positive high voltage, e.g., +21 V, is applied to the erase gate 12. In this state, the Fowler-Nordeheim tunneling effect occurs so that electrons in the floating gate are emitted out to the erase gate to charge the floating gate positive. As a result, the threshold voltage of the memory cell lowers. This condition is assumed as data "1".
The equivalent circuit of the memory cell shown in FIGS. 2A to 2C is shown in FIG. 3, and the capacitive equivalent circuit is shown in FIG. 4. In FIG. 3, V.sub.D represents a drain voltage, V.sub.S represents a source voltage, V.sub.FG represents a floating gate voltage, V.sub.EG represents an erase voltage, and V.sub.CG represents a control gate voltage. In FIG. 4, C.sub.FC represents a capacitance between the floating gate 11 and control gate 13, C.sub.FE represents a capacitance between the floating gate 11 and erase gate 12, C.sub.FD represents a capacitance between the floating gate 11 and drain 15, and C.sub.FS represents another capacitance as viewed from the floating gate 11.
Such memory cells are disposed in a matrix form. For the simplicity of description, a memory cell array MA having four bit memory cells M(A) to M(D) shown in the circuit of FIG. 1 are used illustratively. Drains D of the four memory cells M are connected to two data lines DL1 and DL2, control gates CG are connected to two word lines WL1 and WL2, and erase gates EG of all the memory cells M are connected in common to an erase line EL. A reference voltage, e.g., 0 V, is applied to the source S.
In the memory cell array MA constructed as above, data write to a selected memory cell will be described. Consider the case where data "0" is written to a memory cell M(A) for example. A high voltage +8 V is applied to the data line DL1, and a high voltage +12 V is applied to the word line WL1. The other data line DL2 and word line WL2 are applied with 0 V. In this state, the memory cells M(B) to M(D) are not selected and so not written. A voltage, 0 V or higher, is being applied to the drains, control gates and erase gates of the non-selected memory cells M(B) to M(D). As a result, a voltage stress is applied to the floating gates of non-selected memory cells M(B) to M(D). This voltage stress can be calculated in the following manner.
The initial value Q(I) of electric charge stored in all the capacitors shown in FIG. 4 is given by the following expression (1): EQU Q(I)=(V.sub.FG -V.sub.CG)*C.sub.FC +(V.sub.FG -V.sub.EG)*C.sub.FE +(V.sub.FG -V.sub.D)*C.sub.FD +(V.sub.FG -V.sub.S)*C.sub.FS ( 1)
The total capacitance C.sub.T of all the capacitors shown in FIG. 4 is given by the following expression (2): EQU C.sub.T =C.sub.FC +C.sub.FE +C.sub.FD +C.sub.FS ( 2)
Therefore, the voltage V.sub.FG at the floating gate is given by: EQU V.sub.FG ={(V.sub.CG *C.sub.FC +V.sub.EG *C.sub.FE +V.sub.D *C.sub.FD +V.sub.S *C.sub.FS)/C.sub.T }+[Q(I)/C.sub.T ] (3)
By substituting Q(I)/C.sub.T =V.sub.FG (I) and V.sub.S =0 V, the expression (3) is rewritten by: EQU V.sub.FG ={(V.sub.CG *C.sub.FC +V.sub.EG *C.sub.FE +V.sub.D *C.sub.FD)/C.sub.T }+V.sub.FG (I) (4)
The value of each is capacitor given by: EQU C.sub.FC =(.epsilon..sub.ox *S.sub.C)/t.sub.ox1 ( 5) EQU C.sub.FE =(.epsilon..sub.ox *S.sub.E)/t.sub.ox2 ( 6) EQU C.sub.FD =(.epsilon..sub.ox *S.sub.D)/t.sub.ox3 ( 7) EQU C.sub.FS ={(.epsilon..sub.ox *S.sub.S)/t.sub.ox3 }+{(.epsilon..sub.ox *S.sub.F)/t.sub.ox4 } (8)
where S.sub.C represents an interfacing area between the floating gate 11 and control gate 13, t.sub.ox1 represents a thickness of the insulating film 21 therebetween, S.sub.E represents an interfacing area between the floating gate 11 and erase gate 12, t.sub.ox2 represents a thickness of the insulating film 20 therebetween, S.sub.D represents an interfacing area between the floating gate 11 and drain 16, t.sub.ox3 represents a thickness of the insulating film 19 therebetween, S.sub.S represents an interfacing area between the floating gate 11, and source 15 and channel, S.sub.F represents an interfacing area between the floating gate 11 and field insulating film 24, t.sub.ox4 represents a thickness of the field insulating film 24, and .epsilon..sub.ox represents a dielectric constant of the insulating film.
It is assumed that the memory cell shown in FIGS. 2A to 2C has the following parameters. Namely, for the insulating films, t.sub.ox1 =680 angstroms, t.sub.ox2 =370 angstroms, t.sub.ox3 =280 angstroms, and t.sub.ox4 =8000 angstroms. For the areas, S.sub.C =1.4 mm.sup.2, S.sub.E =0.42 mm.sup.2, S.sub.D =0.3 mm.sup.2, S.sub.S =0.4 mm.sup.2, and S.sub.F =1.12 mm.sup.2. The depth of the diffusion layer is x.sub.j =0.3 .mu.m.
An erroneous operation of the non-selected memory cells M(B) to M(D) during the data write operation will be described in detail with reference to Tables 1 and 2 with V.sub.EG being set to 0 V and 5 V respectively. Given in Tables 1 and 2 are the gate voltages and the voltage stresses of the floating gates calculated by the above expressions of the equivalent circuit.
TABLE 1 ______________________________________ (EG = 5 V) Potential differ- ence Potential V.sub.EG - difference Memory V.sub.FG at V.sub.S -V.sub.FG at cell V.sub.CG V.sub.EG V.sub.D V.sub.S V.sub.FG FG-EG FG-source ______________________________________ A "1" 12 5 8 0 9.68 -4.68 -9.68 "0" 3.68 1.32 -3.68 B "1" 12 5 0 0 8.21 3.21 -8.21 "0" 2.91 2.79 -2.91 C "1" 0 5 8 0 5.44 -0.44 (C) -5.44 "0" -0.56 5.56 0.56 D "1" 0 5 0 0 3.97 1.03 -3.97 "0" -2.03 (D) 7.03 2.03 ______________________________________
TABLE 2 ______________________________________ (EG = 0 V) Potential differ- ence Potential V.sub.EG - difference Memory V.sub.FG at V.sub.S -V.sub.FG at cell V.sub.CG V.sub.EG V.sub.D V.sub.S V.sub.FG FG-EG FG-source ______________________________________ A "1" 12 0 8 0 8.71 -8.71 -8.71 "0" 2.71 -2.71 -2.71 B "1" 12 0 0 0 7.24 (B) -7.24 -7.24 "0" 1.24 -1.24 -1.24 C "1" 0 0 8 0 4.47 -4.47 -4.47 "0" -1.53 1.53 1.53 D "1" 0 0 0 0 3 -3 -3 "0" -3 3 3 ______________________________________
In the non-selected memory cell M(B) of the "1" state, a potential difference (V.sub.EG -V.sub.FG) of -7.24 V appears between the erase gate and floating gate when the erase gate voltage is low (e.g., V.sub.EG =0 V). During data erase, a voltage +10.3 V is applied to the erase gate of the selected memory cell M(A) as viewed from the floating gate. In other words, the non-selected memory cell M(B) is applied with a voltage, opposite in polarity to, and approximately in the order of, the voltage used during the data erase for the selected memory cell. As a result, electrons are injected from the erase gate to the floating gate by the tunneling effect, resulting in a possible write error.
In the non-selected memory cell M(C) of the "1" state, a potential difference (V.sub.S -V.sub.FG) or -5.44 V appears between the source and the floating gate when the erase gate voltage is high (e.g., V.sub.EG =5.0 V), also resulting in a possible write error.
The occurrence rate of write errors is high for memory cells near the selected memory cell M(A). The reason for this will be detailed below.
During data write to the selected memory cell M(A), electrons are accelerated in the region near the drain by the electric field concentrated onto this region, thereby generating high energy electron-hole pairs. The generated holes raise the substrate potential near the memory cell M(A), and therefore lower the threshold voltages V.sub.th of memory cells near the selected memory cell M(A) (e.g., the next memory cell M(C) on the same data line). Therefore, a small cell current will flow, and electrons are injected into the floating gate by the electric field between the substrate and floating gate as described above, resulting in a write error. Of memory cells taking the same condition as the memory cell M(C) (V.sub.EG =5.0 V, V.sub.CG =0 V, V.sub.D =8 V, V.sub.S =0 V, "1" state), the nearer the memory cells to the selected memory cell, the more they are likely to be subject to write errors.
In the non-selected memory cell M(D) of the "0" state, a potential difference (V.sub.EG -V.sub.FG) of 7.03 V appears between the erase gate and floating gate when the erase gate voltage is high (e.g., V.sub.EG =5 V). With this potential difference, electrons are emitted from the floating gate to the erase gate, resulting in a possible erase error.
In Tables 1 and 2, the potential difference (B) indicates a V.sub.EG stress causing a write error of the memory cell M(B), the potential difference (C) indicates a V.sub.EG stress causing a write error of the memory cell M(C), and the potential difference (D) indicates a V.sub.EG stress causing an erase error of the memory cell M(D).
In the above-described memory cell array, it is conventional to set the erase gate voltage to V.sub.EG =V.sub.CC =5.0 V. In such a case, as described previously, a write error may occur in the memory cell M(C) and an erase error may occur in the memory cell M(D). The conventional erase electrode voltage has been determined depending upon V.sub.CC. If V.sub.CC takes a higher voltage than 5.0 V, the write error and erase error of the memory cells M(C) and M(D) will become more likely to occur. For example, in programming by using a ROM writer, the EP compatible mode uses V.sub.CC =6.0 to 6.5 V, and the on-board command mode uses V.sub.CC =4.5 to 5.5 V. In such a case, in the memory cell M(D) of the "0" state, a voltage stress or potential difference between the floating gate and erase gate has a difference of 1.6 V at the maximum. On the other hand, if V.sub.EG is set to 0 V, the write error and erase error of the memory cells M(C) and M(D) are suppressed. However, as described above, in the memory cell M(B), the voltage at the floating gate becomes higher than that at the erase gate, resulting in a possible write error.
As described above, the erase voltage has been determined depending upon V.sub.CC so that the voltage stress changes with V.sub.CC. Therefore, it is difficult to optimize designs and processes allowing the improvement of memory cell reliability.
As stated above, a memory using as memory cells non-volatile transistors having a floating gate, has been associated with erroneous operations of non-selected memory cells to be caused by a voltage stress applied to floating gates.